1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which has been improved in the cell structure and sense amplifier circuit of a dynamic RAM (DRAM).
2. Description of the Related Art
The structure of a memory cell and the read-out and rewrite sequence thereof are as illustrated in FIGS. 1A and 1B, respectively. As illustrated in FIG. 1A, the gate of a cell transistor QM is connected to a word line, the drain thereof is connected to a bit line BL1, and the source thereof is connected to one end of a cell capacitor CM, the other end of which is connected to a plate electrode PL. The memory cell MC composed of the transistor QM and capacitor CM is driven by signals illustrated in FIG. 1B.
When realizing a future increase in the capacitance of DRAMs, it becomes necessary to decrease the power supply voltage in order to suppress an increase in the power consumption and ensure the reliability of the device. However, since an increase in the capacitance is followed by an increase in the current consumption, the above-mentioned conventional memory cell structure and read-out and rewrite method make it difficult to suppress the power consumption. Also, in the above-mentioned conventional memory cell, if the cell capacitance is constant, the quantity of a read-out signal decreases as the power supply voltage decreases. However, when taking it into consideration that the sensitivity of the sense amplifier has a lower limit, that the quantity of signal decreases due to .alpha.-rays, etc., a certain level and quantity of read-out signal is indispensable. This makes it necessary to increase the capacitance of the capacitor.
Meanwhile, as a sense amplifier which has been most widely employed as that of a DRAM, there is a flip-flop sense amplifier illustrated in FIG. 2. This sense amplifier has, on one hand, merits in that the circuit construction thereof is simple, etc., but has, on the other hand, a demerit in that a period necessary for performance of the sensing operation is significantly large. Also, when causing a decrease in the level of the power supply voltage which will be demanded to be realized in future, since the potential difference between the gate and source of four transistors Qn1, Qn2, Qp1 and Qp2 constituting the sense amplifier can be set to only 1/2 of the power supply voltage even at maximum and since it is not real to largely decrease the threshold value voltage of the transistor, the sensing operation will become again lower in speed.
For example, when the amplitude of the bit line potential is set to be 1 V, only a potential difference of 0.5 V in a worst case can be obtained between the gate and source of the sense amplifier transistors. Assuming that the threshold value voltage of the n-type transistors Qn1 and Qn2 is 0.6 V and the threshold value voltage of the p-type transistors Qp1 and Qp2 is -0.6 V, each of these transistors can no longer be operated but in a sub-threshold region, with the result that the sensing period of time largely increases, whereby a practical sensing speed can not be obtained.
Also, since the potential of the sense amplifier drive lines at a sensing time is equal to a potential for writing data into the memory cell, the both potentials can not be optimized in the form wherein they are different from each other.
As mentioned above, in the conventional DRAM, when decreasing the power supply voltage, the quantity of read-out signal for reading out data from the memory cell decreases in proportion thereto. When increasing the capacitance of the cell capacitor for the purpose of increasing the quantity of read-out signal, problems of increasing difficulty of cell capacity forming techniques, increase of cost and so on occur.
Also, in the conventional flip-flop sense amplifier, the sensing period of time is significantly large and, in addition, it is difficult to decrease the level of the power supply voltage. These problems arise from the fact that because the gates of the four transistors constituting the sense amplifier are connected to the bit lines, the potential difference between the gates of the operating transistors and the sense amplifier drive lines is impossible to obtain sufficiently.